MOS Scaling

In this chapter will be discussed the problem of scaling in MOS technology, from the constant field scaling and the rules behind it, the short channel effects and all the considerations about it.

Constant field scaling

One of the main issues with reducing the dimensions of a MOSFET is the high electric fields, like in the channel of , with a even with a of 1V leads to a field. To avoid this issue, the safe way to scale the device is the Dennard scaling, maintaining the electric field constant: by scaling all the device dimensions and all the voltages by the same scaling factor .

Where is the thickness of the oxide, is the length of the gate, is the width of the MOS, is the depth of the source and drain wells and is the voltage applied (this is valid for all voltages applied to the “scaled” MOS)

Not only the geometrical and electrical parameters must be scaled, to maintain the electric field unchanged (in the depletion region), but also the doping concentration must change, and we need to increase it by the same factor . This is because the solution of Poisson’s equation must maintain the same solution:

One of the main problems while scaling devices is the dissipated power, in order to keep constant the dissipated power per unit area, scaling the device by , means that the area is scaled by and so the dissipated power must scale of the same factor of the area, but in the process there are some issues.

The OFF current

todo add link The current of a MOS transistor (recalling the expression found in chapter 03) is:

that when

So the OFF current increases exponentially while decreasing the threshold voltage The parameter decreases linearly () with so it cannot compensate the increase of the OFF current. In order to restore an acceptable OFF current, a short device should have a higher slope so lower , but capacitances scale by the same factor, and so is constant therefore is constant. The dissipated power/chip with should not exceed 1W and considering a circuit with devices at a voltage of 1V, so the OFF current should be . It is also required ahigh ON/OFF ratio, a common criteria is that the current at threshold () should be at least 100 times the current OFF, that can be obtained choosing a proper .

Considering a safe choice for the minimum of the voltage threshold

The ON current

The speed of integrated circuit increases with higher current ()

and a common criteria to ensure a good ON current is to take:

and the threshold voltage is a trade-off between high power dissipation and speed.

Short Channel Effects (SCE)

SCEs are experimental phenomena observed decreasing only. Even though is independent from but the most important effect is the lowering of with decreasing , called roll-off. This effect is enhanced as grows.

The explanation can be traced back to the electric field distribution, which becomes fully 2-dimensional, so the GCA is no longer verified.

Looking at the equipotential lines when is slightly below threshold and is high:

• In a long device the equipotential lines are horizontal under the gate, apart from the corner regions close to the source and drain pn junctions and are close to the gate ( is really high) and close to the Si surface
• In a short device the equipotential lines are not horizontal ( under the channel) and less close to the gate, is lower and spread away from the Si surface.

In the image below we can see that below threshold () the surface potential in the short channel is higher, and the energy barrier is lower with respect to the “long” channel case.

If a voltage is applied between source and drain (>0) the voltage on the drain increases and in a short channel MOS the surface voltage increases, and the energy barrier decreases even more. This effect is called Drain Induced Barrier Lowering (DIBL)

Taking into account all the listed phenomena: In order to minimize the Short Channel Effects is known that the condition is To minimize :

To avoid breakdown in the oxide the field must be less than

And finally to avoid OFF power dissipation (considering also the speed of the device)

with all these constraints it is impossible to design a device, the device structure must change.